SN54LS280 Datasheet, PDF (1/4 Pages) Motorola, Inc – 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

9-BIT ODD/EVEN PARITY
GENERATORS/CHECKERS
The SN54/ 74LS280 is a Universal 9-Bit Parity Generator / Checker. It fea-
tures odd / even outputs to facilitate either odd or even parity. By cascading,
the word length is easily expanded.
The LS280 is designed without the expander input implementation, but the
corresponding function is provided by an input at Pin 4 and the absence of any
connection at Pin 3. This design permits the LS280 to be substituted for the
LS180 which results in improved performance. The LS280 has buffered
inputs to lower the drive requirements to one LS unit load.
• Generates Either Odd or Even Parity for Nine Data Lines
• Typical Data-to-Output Delay of only 33 ns
• Cascadable for n-Bits
• Can Be Used To Upgrade Systems Using MSI Parity Circuits
• Typical Power Dissipation = 80 mW
INPUTS
VCC F
E
D
C
B
A
14 13 12 11 10 9
8
F
ED
CB
G
A
∑∑
H
I EVEN ODD
12
GH
INPUTS
3
4
5
6
7
NC I
∑ ∑ GND
INPUT EVEN ODD
OUTPUTS
FUNCTION TABLE
NUMBER OF INPUTS A
THRU 1 THAT ARE HIGH
OUTPUTS
∑EVEN ∑ODD
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
L
H
H = HIGH Level, L = LOW Level
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Ambient Temperature Range
IOH
Output Current — High
IOL
Output Current — Low
54
74
54
74
54, 74
54
74
SN54/74LS280
9-BIT ODD/ EVEN PARITY
GENERATORS/ CHECKERS
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
Min
Typ
Max
Unit
4.5
5.0
5.5
V
4.75
5.0
5.25
– 55
25
125
°C
0
25
70
– 0.4
mA
4.0
mA
8.0
FAST AND LS TTL DATA
5-456