SN54LS175 Datasheet, PDF (1/5 Pages) Motorola, Inc – QUAD D FLIP-FLOP

QUAD D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
1
2
3
4
5
6
78
MR Q0 Q0 D0 D1 Q1 Q1 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs (Note b)
Complemented Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
MR CP D3
D2
D1
D0
1 9 13
12
5
4
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
VCC = PIN 16
GND = PIN 8
14
15
Q3 Q3
= PIN NUMBERS
11
10
Q2 Q2
6
7
Q1Q1
3
2
Q0 Q0
SN54/74LS175
QUAD D FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
5
12
13
D0
D1
D2
D3
9
CP
1
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
3 2 6 7 11 10 14 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-327