SN54LS166 Datasheet, PDF (1/4 Pages) Motorola, Inc – 8-BIT SHIFT REGISTERS

8-BIT SHIFT REGISTERS
The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54/ 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and has a
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode.
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command with
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
• Synchronous Load
• Direct Overriding Clear
• Parallel to Serial Conversion
PARALLEL PARALLEL INPUTS
SHIFT/ INPUT OUTPUT
VCC _LOAD H QH G F E CLEAR
16 15 14 13 12 11 10 9
SHIFT/ H QH
LOAD
SERIAL INPUT
A BC
GF E
CLEAR
D
CLOCK
INHIBIT
CK
1
SERIAL
INPUT
2345
AB CD
PARALLEL INPUTS
6 78
CLOCK CLOCK GND
INHIBIT
SN54/74LS166
8-BIT SHIFT REGISTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
SHIFT/
CLEAR _LOAD
L
X
H
X
H
L
H
H
H
H
H
X
FUNCTION TABLE
INPUTS
CLOCK
PARALLEL
INHIBIT ^{CLOCK SERIAL}
A...H
X
X
X
X
L
L
X
X
L
↑
X
a...h
L
↑
H
X
L
↑
L
X
H
↑
X
X
INTERNAL
OUTPUTS
QA
L
QA0
a
H
L
QA0
QB
L
QB0
b
QAn
QAn
QB0
OUTPUT
QH
L
QH0
h
QGn
QGn
QH0
FAST AND LS TTL DATA
5-1