SN5474LS114A Datasheet, PDF (1/4 Pages) Motorola, Inc – DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may be allowed to change when
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.
SN54/74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
CLEAR (CD)
TO
OTHER
FLIPĆFLOP
J
3(11)
13
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
INPUTS
SD CD J
LHX
HLX
LLX
HH h
HH l
HH h
HH l
OUTPUTS
KQQ
XHL
XLH
XHH
hqq
h LH
l HL
l
q
q
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
Q
6(8)
14
1
J SUFFIX
CERAMIC
CASE 632-08
4(10)
SET (SD)
K
2(12)
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4
10
SD
3
J
Q
13
CP
2
K _CD ^Q
11
SD
5
J
Q
9
CP
12
6
K
Q
CD
8
1
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-193