MTP7N20E Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 7.0 AMPERES 200 VOLTS RDS(on) = 0.70 OHMS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
™ Designer's Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
®
D
S
Order this document
by MTP7N20E/D
MTP7N20E
Motorola Preferred Device
TMOS POWER FET
7.0 AMPERES
200 VOLTS
RDS(on) = 0.70 OHMS
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VDSS
VDGR
VGS
VGSM
200
Vdc
200
Vdc
± 20
Vdc
± 40
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
ID
7.0
Adc
ID
3.8
IDM
21
Apk
PD
50
Watts
0.4
W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 Ω)
TJ, Tstg
– 55 to 150
°C
EAS
mJ
74
Thermal Resistance — Junction to Case°
— Junction to Ambient°
R_θJC
R_θJA
2.5°
62.5°
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
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