MTP50P03HDL Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS RDS(on) = 0.025 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
™ Designer's Data Sheet
HDTMOS E-FET.™
Power Field Effect Transistor
P–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
D
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MTP50P03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
RDS(on) = 0.025 OHM
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
G
CASE 221A–06, Style 5
TO–220AB
S
Symbol Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VDSS
30
Vdc
VDGR
30
Vdc
VGS
± 15
Vdc
VGSM
± 20
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
ID
50
Adc
ID
31
IDM
150
Apk
PD
125
Watts
1.0
W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 Ω)
TJ, Tstg – 55 to 150 °C
EAS
1250
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
R_θJC
R_θJA
TL
1.0
°C/W
62.5
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
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