MTP2955V Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.230 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
™ Designer's Data Sheet
TMOS V^™
Power Field Effect Transistor
P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
G
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
TM
D
S
Order this document
by MTP2955V/D
MTP2955V
TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.230 OHM
CASE 221A–09, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
60
Vdc
± 15
Vdc
± 25
Vpk
12
Adc
8.0
42
Apk
60
Watts
0.40
W/°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)
EAS
216
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R_θJC
R_θJA
2.5
°C/W
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 3
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