MTP12P10 Datasheet, PDF (1/6 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 100 VOLTS RDS(on) = 0.3 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
™ Designer's Data Sheet
Power Field Effect Transistor
P–Channel Enhancement–Mode Silicon Gate
This TMOS Power FET is designed for medium voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds — Switching Times
Specified at 100°C
• Designer’s Data — IDSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
• Rugged — SOA is Power Dissipation Limited
• Source–to–Drain Diode Characterized for Use With Inductive Loads
®
D
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by MTP12P10/D
MTP12P10
TMOS POWER FET
12 AMPERES
100 VOLTS
RDS(on) = 0.3 OHM
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive (tp ≤ 50 µs)
Drain Current — Continuous
Drain Current — Pulsed
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
CASE 221A–06, Style 5
TO–220AB
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
R_θJC
R_θJA
TL
Value
100
100
± 20
± 40
12
28
75
0.6
– 65 to 150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Watts
W/°C
°C
1.67
°C/W
62.5
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc.
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