MTP12N10E Datasheet, PDF (1/6 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 100 VOLTS RDS(on) = 0.16 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTP12N10E/D
™ Designer's Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Designed to Eliminate the Need for External Zener Transient
Suppressor — Absorbs High Energy in the Avalanche Mode
• Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
G
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
MTP12N10E
Motorola Preferred Device
®
D
TMOS POWER FET
12 AMPERES
100 VOLTS
RDS(on) = 0.16 OHM
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 µs)
Drain Current — Continuous
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
VDSS
VDGR
VGS
ID
IDM
PD
Operating and Storage Temperature Range
TJ, Tstg
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ ≤ 175°C)
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 Ω, Peak IL = 12 A)
(See Figures 15, 16 and 17)
EAS
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
R_θJC
R_θJA
TL
CASE 221A–06, Style 5
TO–220AB
Value
100
100
± 20
± 40
12
30
79
0.53
– 55 to 175
Unit
Vdc
Vdc
Vdc
Adc
Watts
W/°C
°C
290
mJ
1.9
°C/W
62.5
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
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