MTP12N06EZL Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.180 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
™ Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche mode and switch efficiently. This new high
energy device also offers a gate–to–source zener diode designed
for 4 kV ESD protection (human body model).
• ESD Protected
• 4 kV Human Body Model
• 400 V Machine Model
• Avalanche Energy Capability
• Internal Source–To–Drain Diode Designed to Replace External
Zener Transient Suppressor–Absorbs High Energy in the
Avalanche Mode
G
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MTP12N06EZL
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TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.180 OHM
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
60
Vdc
± 15
Vdc
± 20
Vpk
12
Adc
7.1
36
Apk
45
Watts
0.36
W/°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
72
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
R_θJC
R_θJA
2.78
°C/W
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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