MTP10N40E Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 10 AMPERES 400 VOLTS RDS(on) = 0.55 OHMS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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™ Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
G
Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
MTP10N40E
TMOS POWER FET
10 AMPERES
400 VOLTS
RDS(on) = 0.55 OHMS
®
D
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive
VDSS
VDGR
VGS
VGSM
Drain Current — Continuous
ID
Drain Current — Pulsed
IDM
Total Power Dissipation
PD
Derate above 25°C
Operating and Storage Temperature Range
TJ, Tstg
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C
Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain–to–Source Avalanche Energy
WDSR(1)
WDSR(2)
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
(1) VDD = 50 V, ID = 10 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
R_θJC
R_θJA
TL
CASE 221A–06, Style 5
TO-220AB
Value
400
400
± 20
± 40
10
40
125
1.0
– 65 to 150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Watts
W/°C
°C
520
mJ
83
13
1.0
°C/W
62.5
275
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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