MTP10N10EL Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 10 AMPERES 100 VOLTS RDS(on) = 0.22 OHMS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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™ Designer's Data Sheet
Logic Level TMOS E-FET.™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
®
D
S
MTP10N10EL
Motorola Preferred Device
TMOS POWER FET
10 AMPERES
100 VOLTS
RDS(on) = 0.22 OHMS
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
100
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
Vdc
± 20
Vpk
Drain Current — Continuous @ TC = 25°C
— Continuous @ TC = 100°C
— Single Pulse (tp ≤ 10 µs)
ID
10
Adc
ID
6.0
IDM
35
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TC = 25°C ⁽¹⁾
PD
40
Watts
0.32
W/°C
1.75
Watts
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 10 Adc, L = 1.0 mH, RG = 25 Ω)
EAS
mJ
50
Thermal Resistance — Junction to Case°
— Junction to Ambient
— Junction to Ambient ⁽¹⁾
R_θJC
R_θJA
R_θJA
3.13
°C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
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