MTD5P06V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 5 AMPERES 60 VOLTS RDS(on) = 0.450 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD5P06V/D
™ Designer's Data Sheet
TMOS V.™
Power Field Effect Transistor
MTD5P06V
Motorola Preferred Device
DPAK for Surface Mount
P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
TM
D
TMOS POWER FET
5 AMPERES
60 VOLTS
RDS(on) = 0.450 OHM
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
G
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
S
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel,
Add –T4 Suffix to Part Number
CASE 369A–13, Style 2
DPAK Surface Mount
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
60
± 15
± 25
5
4
18
40
0.27
2.1
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 5 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TJ, Tstg
EAS
R_θJC
R_θJA
R_θJA
TL
– 55 to 175
125
3.75
100
71.4
260
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
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