MTD3055V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.15 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD3055V/D
™ Designer's Data Sheet
TMOS V
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
G
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
TM
D
S
MTD3055V
Motorola Preferred Device
TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.15 OHM
CASE 369A–13, Style 2
DPAK
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate–Source Voltage – Continuous
Gate–Source Voltage – Non–repetitive (tp ≤ 10 ms)
VGS
± 20
Vdc
VGSM
± 25
Vpk
Drain Current – Continuous @ 25°C
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (tp ≤ 10 µs)
ID
12
Adc
ID
7.3
IDM
37
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD
48
Watts
0.32
W/°C
1.75
Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 Ω )
EAS
72
mJ
Thermal Resistance – Junction to Case
R_θJC
3.13
°C/W
Thermal Resistance – Junction to Ambient
R_θJA
100
Thermal Resistance – Junction to Ambient, when mounted to minimum recommended pad size
R_θJA
71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© ^MMo^oto^toro^rl^oa,^laInc^T.^M19^O96^{S Power MOSFET Transistor Device Data}
1