MTD2N40E Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 2.0 AMPERES 400 VOLTS RDS(on) = 3.5 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD2N40E/D
™ Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche and switch efficiently. This
new high energy device also offers a drain–to–soure diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
G
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add –T4 Suffix to Part Number
• Replaces MTD1N40E
®
D
S
MTD2N40E
Motorola Preferred Device
TMOS POWER FET
2.0 AMPERES
400 VOLTS
RDS(on) = 3.5 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
400
Vdc
VDGR
400
Vdc
VGS
± 20
Vdc
VGSM
± 40
Vpk
Drain Current — Continuous @ TC = 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
2.0
Adc
ID
1.5
IDM
6.0
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted to minimum recommended pad size
PD
40
Watts
0.32
W/°C
1.75
Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
EAS
45
mJ
Thermal Resistance — Junction to Case
R_θJC
3.13
°C/W
Thermal Resistance — Junction to Ambient
R_θJA
100
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
R_θJA
71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
© ^MMo^oto^toro^rl^oa,^laInc^T.^M19^O95^{S Power MOSFET Transistor Device Data}
1