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MTD2955V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.230 OHM | |||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD2955V/D
⢠Designer's Data Sheet
TMOS Vâ¢
Power Field Effect Transistor
DPAK for Surface Mount
PâChannel EnhancementâMode Silicon Gate
TMOS V is a new technology designed to achieve an onâresis-
tance area product about oneâhalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EâFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
G
⢠Onâresistance Area Product about Oneâhalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
⢠Faster Switching than EâFET Predecessors
MTD2955V
TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.230 OHM
TM
D
CASE 369Aâ13, Style 2
S
DPAK Surface Mount
Features Common to TMOS V and TMOS EâFETS
⢠Avalanche Energy Specified
⢠IDSS and VDS(on) Specified at Elevated Temperature
⢠Static Parameters are the Same for both TMOS V and TMOS EâFET
⢠Surface Mount Package Available in 16 mm 13âinch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainâtoâSource Voltage
DrainâtoâGate Voltage (RGS = 1.0 Mâ¦)
GateâtoâSource Voltage â Continuous
GateâtoâSource Voltage â Nonârepetitive (tp ⤠10 ms)
VDSS
60
Vdc
VDGR
60
Vdc
VGS
± 15
Vdc
VGSM
± 25
Vpk
Drain Current â Continuous
Drain Current â Continuous @ 100°C
Drain Current â Single Pulse (tp ⤠10 µs)
ID
12
Adc
ID
8.0
IDM
42
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C(1)
PD
60
Watts
0.4
W/°C
2.1
Watts
Operating and Storage Temperature Range
Single Pulse DrainâtoâSource Avalanche Energy â Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 â¦)
Thermal Resistance â Junction to Case
Thermal Resistance â Junction to Ambient
Thermal Resistance â Junction to Ambient(1)
Maximum Lead Temperature for Soldering Purposes, 1/8â³ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
â 55 to 175
216
2.5
100
71.4
260
°C
mJ
°C/W
°C
Designerâs Data for âWorst Caseâ Conditions â The Designerâs Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves â representing boundaries on device characteristics â are given to facilitate âworst caseâ design.
EâFET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 3
© MMoototororloa,laIncT.M19O97S Power MOSFET Transistor Device Data
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