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MTD15N06V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 15 AMPERES 60 VOLTS | |||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD15N06V/D
⢠Designer's Data Sheet
TMOS V
Power Field Effect Transistor
DPAK for Surface Mount
NâChannel EnhancementâMode Silicon Gate
TMOS V is a new technology designed to achieve an onâresis-
tance area product about oneâhalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EâFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
MTD15N06V
Motorola Preferred Device
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
TM
D
New Features of TMOS V
⢠Onâresistance Area Product about Oneâhalf that of Standard
G
MOSFETs with New Low Voltage, Low RDS(on) Technology
⢠Faster Switching than EâFET Predecessors
CASE 369Aâ13, Style 2
DPAK Surface Mount
S
Features Common to TMOS V and TMOS EâFETS
⢠Avalanche Energy Specified
⢠IDSS and VDS(on) Specified at Elevated Temperature
⢠Static Parameters are the Same for both TMOS V and TMOS EâFET
⢠Surface Mount Package Available in 16 mm 13âinch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainâSource Voltage
VDSS
60
Vdc
DrainâGate Voltage (RGS = 1.0 Mâ¦)
VDGR
60
Vdc
GateâSource Voltage â Continuous
GateâSource Voltage â Single Pulse (tp ⤠50 ms)
VGS
± 20
Vdc
VGSM
± 25
Vpk
Drain Current â Continuous @ 25°C
Drain Current â Continuous @ 100°C
Drain Current â Single Pulse (tp ⤠10 µs)
ID
15
Adc
ID
8.7
IDM
45
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD
55
Watts
0.36
W/°C
2.1
Watts
Operating and Storage Temperature Range
TJ, Tstg â 55 to 175
°C
Single Pulse DrainâtoâSource Avalanche Energy â Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 â¦)
EAS
113
mJ
Thermal Resistance â Junction to Case
RθJC
2.73
°C/W
Thermal Resistance â Junction to Ambient
RθJA
100
Thermal Resistance â Junction to Ambient, when mounted to minimum recommended pad size
RθJA
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8â³ from case for 10 seconds
TL
260
°C
Designerâs Data for âWorst Caseâ Conditions â The Designerâs Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves â representing boundaries on device characteristics â are given to facilitate âworst caseâ design.
EâFET, Designerâs and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
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