MTB8N50E Datasheet, PDF (1/6 Pages) Motorola, Inc – TMOS POWER FET 8.0 AMPERES 500 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB8N50E/D
™ Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
G
against unexpected voltage transients.
®
D
• Robust High Voltage Termination
S
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured – Not Sheared
• Specifically Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MTB8N50E
TMOS POWER FET
8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
W Drain–to–Gate Voltage (RGS = 1.0 M )
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms)
VDSS
VDGR
VGS
VGSM
500
Vdc
500
Vdc
±20
Vdc
±40
Vpk
Drain Current — Continuous @ TC = 25°C
m ^{Drain Current — Continuous @ TC = 100°C}
Drain Current — Single Pulse (tp ≤ 10 s)
ID
8.0
Adc
ID
5.0
IDM
32
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
125
Watts
1.0
W/°C
Operating and Storage Temperature Range
W Single Pulse Drain–to–Source Avalanche Energy – STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25 )
TJ, Tstg
– 55 to 150
°C
EAS
510
mJ
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient ⁽¹⁾
R_qJC
R_qJA
R_qJA
1.0
°C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 sec.
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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