MTB6N60E Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 6.0 AMPERES 600 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB6N60E/D
™ Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain–to–source diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
G
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
®
D
S
MTB6N60E
Motorola Preferred Device
TMOS POWER FET
6.0 AMPERES
600 VOLTS
RDS(on) = 1.2 OHM
CASE 418B–03, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
600
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
600
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
± 20
Vdc
VGSM
± 40
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
6.0
Adc
ID
4.6
IDM
18
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C ⁽¹⁾
PD
125
Watts
1.0
W/°C
2.5
Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 Ω)
EAS
mJ
405
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient ⁽¹⁾
R_θJC
R_θJA
R_θJA
1.0
°C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
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