MTB52N06V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 52 AMPERES 60 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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™ Designer's Data Sheet
TMOS V™
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
G
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETs
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MTB52N06V
Motorola Preferred Device
TMOS POWER FET
52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM
TM
D
CASE 418B–02, Style 2
S
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
60
Vdc
VDGR
60
Vdc
VGS
± 20
Vdc
VGSM
± 25
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
52
Adc
ID
41
IDM
182
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD
188
Watts
1.25
W/°C
3.0
Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 Ω)
EAS
406
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R_θJC
R_θJA
R_θJA
0.8
°C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
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