MTB1306 Datasheet, PDF (1/8 Pages) Motorola, Inc – TMOS POWER FET 75 AMPERES

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
HDTMOS E-FET.™
High Density Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Order this document
by MTB1306/D
MTB1306
TMOS POWER FET
75 AMPERES
30 VOLTS
RDS(on) = 0.0065 OHM
CASE 418B–03
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C ⁽¹⁾
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
Thermal Resistance — Junction–to–Case
— Junction–to–Ambient
— Junction–to–Ambient ⁽¹⁾
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
EAS
R_θJC
R_θJA
R_θJA
TL
Value
30
30
± 20
± 20
75
59
225
150
1.2
2.5
– 55 to 150
280
0.8
62.5
50
260
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
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Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
1