MRFIC2006 Datasheet, PDF (1/8 Pages) Motorola, Inc – 900 MHz 2 STAGE PA SILICON MONOLITHIC INTEGRATED CIRCUIT

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
The MRFIC Line
900 MHz 2 Stage PA
The MRFIC2006 is an Integrated PA designed for linear operation in the 800
MHz to 1.0 GHz frequency range. The design utilizes Motorola’s advanced
MOSAIC 3 silicon bipolar RF process to yield superior performance in a cost
effective monolithic device. Applications for the MRFIC2006 include CT-1 and
CT-2 cordless telephones, remote controls, video and audio short range links,
low cost cellular radios, and ISM band transmitters.
• 50 Ω Input and Output Impedance
• Typical Gain = 23 dB @ 900 MHz
• Bias Current Externally Adjustable
• Bias Pin can be used to Ramp or Disable
• Class A or AB Linear Operation
• Unconditionally Stable
• SO-8 Leaded Plastic Package
• Order MRFIC2006R2 for Tape and Reel.
R2 Suffix = 2,500 Units per 12 mm, 13 inch Reel.
• Device Marking = M2006
Order this document
by MRFIC2006/D
MRFIC2006
900 MHz 2 STAGE PA
SILICON MONOLITHIC
INTEGRATED CIRCUIT
CASE 751-05
(SO-8)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Zo = 50 Ω unless otherwise noted)
Rating
Symbol
Supply Voltages
VCC1, VCC2
Bias Voltage
Vbias
Total Supply Current
ICC1, ICC2
RF Output Power (VCC2 < 4.0 V)
Pout
RF Output Power (4.0 V < VCC2 ≤ 5.0 V)
Pout
RF Input Power
Pin
Operating Ambient Temperature
TA
Storage and Junction Temperature
Tstg
Thermal Resistance, Junction to Case
R_θJC
Value
5.0
6.0
100
+21
53 – 8 VCC2
+10
– 35 to + 85
– 65 to +150
63
GND
GND
GND
RF OUT (VCC2)
4
3
2
1
Unit
Vdc
Vdc
mA
dBm
dBm
dBm
°C
°C
°C/W
5
6
7
8
RF IN
GND
VCC1
Vbias
Pin Connections and Functional Block Diagram
REV 2
©MMOotoTrOolaR, OIncL.A19R97F DEVICE DATA
MRFIC2006
1