MRFIC0914 Datasheet, PDF (1/6 Pages) Motorola, Inc – 900 MHz PAGING POWER AMPLIFIER Si MONOLITHIC INTEGRATED CIRCUIT

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
The MRFIC Line
900 MHz LDMOS Integrated
Power Amplifier
This integrated circuit is intended for two–way paging applications and for
other Industrial, Scientific and Medical (ISM) at 900 MHz band applications.
The three stage design is implemented in Motorola’s low cost, high perfor-
mance LDMOS process and housed in a low–cost surface mount SOIC
package. Input and output matching is implemented off–chip for maximum
flexibility while interstage matching is on–chip. A power control pin is included
allowing 60 dB dynamic range.
• 30.5 dBm Output Power for 3 dBm Input Power at 900 MHz
• 32 dB Typ Small Signal Gain
• 40% Efficiency Min at 30.5 dBm Output Power
• 4.0 to 5.5 Volt Operation
• Low–Cost, Low Profile Plastic SOIC Package
• Order MRFIC0914R2 for Tape and Reel.
R2 Suffix = 2,500 Units per 16 mm, 13 inch Reel.
• Device Marking = M0914
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Supply Voltage
Supply Current
Power Control Voltage
Input Power
Ambient Operating Temperature
Storage Temperature
Thermal Resistance, Junction to Case
Symbol
VD1, VD2, VD3
IDtotal
VCNTRL
Pin
TA
Tstg
θ_JC
Order this document
by MRFIC0914/D
MRFIC0914
900 MHz PAGING
POWER AMPLIFIER
Si MONOLITHIC
INTEGRATED CIRCUIT
CASE 751B–05
(SOIC–16)
Value
9
2
4.8
6
– 30 to + 80
– 65 to +150
26
Unit
Vdc
Adc
Vdc
dBm
°C
°C
°C/W
VCNTRL 1
GND 2
VD2 3
GND 4
GND 5
RF OUT/VD3 6
GND 7
GND 8
CONTROL
16 GND
15 GND
14 RF IN
13 GND
12 GND
11 VD1
10 GND
9 GND
Pin Connections and Functional Block Diagram
REV 2
©MOMoTtoOroRlaO, ILncA. 1R99F7 DEVICE DATA
MRFIC0914
1