MRF255PHT Datasheet, PDF (1/4 Pages) Motorola, Inc – RF Power Field-Effect Transistor

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
The RF MOSFET Line
RF Power
Field-Effect Transistor
N–Channel Enhancement–Mode
Order this document
by MRF255PHT/D
MRF255
PHOTOMASTER
CASE 211–11, STYLE 2
VGG
+
C5
C6
RF ^{N1 C1}
INPUT
L1
C2
C4
L2
C3
C7
DUT
R2
C9
R1
L5
C8
L3
C10
RFC1
+
C15 C16
+
VDD
C17
L4
C14 ^N2 _RF
OUTPUT
C11
C12
C1 — 470 pF, Chip Capacitor
C2, C3, C11, C12 — 20 – 200 pF, Trimmer, ARCO #464
C4 — 100 pF, Chip Capacitor
C5, C17 — 100 µF, 15 V, Electrolytic
C6 — 0.001 µF, Disc Ceramic
C7, C8, C9, C10 — 330 pF, Chip Capacitor
C14 — 1200 pF, ATC Chip Capacitor
C15 — 910 pF, 500 V, Dipped Mica
C16 — 47 µF, 16 V, Electrolytic
L1 — 8 Turns, #20 AWG, 0.126″ ID
L2 — 5 Turns, #18 AWG, 0.142″ ID
L3 — 3 Turns, #20 AWG, 0.102″ ID
L4 — 7 Turns, #24 AWG, 0.070″ ID
L5 — 6.5 Turns, #18 AWG, 0.230″ ID, 0.5″ Long
N1, N2 — Type N Flange Mount
RFC1 — Ferroxcube VK–200–19/4B
R1 — 39 kΩ, 1/4 W Carbon
R2 — 150 Ω, 1/4 W Carbon
Board — G–10 .060″
Figure 1. 54 MHz Linear RF Test Circuit Electrical Schematic
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling
and packaging MOS devices should be observed.
REV 1
©MMOotTorOolRa,OInLc.A19R96F DEVICE DATA
MRF255 PHOTOMASTER
1