MPC9993 Datasheet, PDF (1/8 Pages) Motorola, Inc – INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9993/D
Rev 1, 04/2003
Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
MPC9993
The MPC9993 is a PLL clock driver designed specifically for redundant
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 2x, phase aligned clock outputs.
Features:
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32–Lead LQFP Packaging
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
PLL_En
Clk_Selected
Inp1bad
Inp0bad
Man_Override
Dynamic Switch
Logic
Alarm_Reset
Qb0
Qb0
Sel_Clk
OR
Qb1
CLK0
Qb1
CLK0
CLK1
Qb2
÷8
Qb2
CLK1
PLL
÷16
Qa0
Ext_FB
Qa0
Ext_FB
800 – 1600 MHz
Qa1
Qa1
MR
Figure 1. Block Diagram
© Motorola, Inc. 2003
1