MPC993 Datasheet, PDF (1/6 Pages) Motorola, Inc – Dynamic Switch PLL Clock Driver

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dynamic Switch
PLL Clock Driver
MPC993
The MPC993 is a PLL clock driver designed specifically for redundant
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer
performance.
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control/Statis I/O
• 3.3V Operation
• 32–Lead TQFP Packaging
• ±50ps Cycle–Cycle Jitter
FA SUFFIX
32–LEAD PLASTIC TQFP PACKAGE
CASE 751D–04
The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty
input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will
automatically switch from the bad reference clock input to the good one. During this dynamic switch of the input references, the
MPC993 outputs will slew, with minimal period disturbances to the new phase.
Dynamic Switch
Qb0
Logic
Qb0
Sel_Clk
OR
Qb1
CLK0
PLL_En
Qb1
CLK0
CLK1
CLK1
÷2
Qb2
Qb2
PLL
÷4
Qa0
Ext_FB
Qa0
Ext_FB
Qa1
Qa1
MR
Figure 1. Block Diagram
9/97
© Motorola, Inc. 1997
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