MPC9893 Datasheet, PDF (1/16 Pages) Motorola, Inc – Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch

MOTOROLA
SEMICONDUCTOR
TECHN^FI^rC^eA^eL^sD^cA^aTA^le
Semiconductor,
Inc. Document Number: MPC9893/D
Rev 3, 01/2004
Low Voltage PLL Intelligent
Dynamic Clock (IDCS) Switch
MPC9893
The MPC9893 is a 2.5V and 3.3V compatible, PLL based intelligent
dynamic clock switch and generator specifically designed for redundant
clock distribution systems. The device receives two LVCMOS clock
signals and generates 12 phase aligned output clocks. The MPC9893 is
able to detect a failing reference clock signal and to dynamically switch to
a redundant clock signal. The switch from the failing clock to the
redundant clock occurs without interruption of the output clock signal
(output clock slews to alignment). The phase bump typically caused by a
clock failure is eliminated.
The device offers 12 low skew clock outputs organized into two output
banks, each configurable to support the different clock frequencies.
The extended temperature range of the MPC9893 supports
telecommunication and networking requirements. The device employs a
fully differential PLL design to minimize jitter.
Features
• 12 output LVCMOS PLL clock generator
• 2.5V and 3.3V compatible
• IDCS - on-chip intelligent dynamic clock switch
• Automatically detects clock failure
• Smooth output phase transition during clock failover switch
• 7.5 - 200 MHz output frequency range
• LVCMOS compatible inputs and outputs
• External feedback enables zero-delay configurations
• Supports networking, telecommunications and computer applications
• Output enable/disable and static test mode (PLL bypass)
• Low skew characteristics: maximum 50 ps output-to-output (within bank)
• 48 lead LQFP package
• Ambient operating temperature range of --40 to 85°C
LOW VOLTAGE 2.5V AND 3.3V
IDCS AND PLL
CLOCK GENERATOR
FA SUFFIX
48--LEAD LQFP PACKAGE
CASE 932
Functional Description
The MPC9893 is a 3.3V or 2.5V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated
PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,
three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same
frequency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency
multiplication of the input reference clock by 3÷2 and 1÷2. Bank A and bank B outputs are phase-aligned¹. Due to the external
PLL feedback, the clock signals of both output banks are also phase-aligned¹ to the selected input reference clock, providing
virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure
individually for each clock input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input,
forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are
interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides a manual mode that
allows for user-controlled clock switches.
The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the
MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be
disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On
power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for
power-on sequence recommendations.
The device is packaged in a 7x7 mm² 48-lead LQFP package.
1. At coincident rising edges
© Motorola, Inc. 2004
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