MPC958 Datasheet, PDF (1/8 Pages) Motorola, Inc – LOW VOLTAGE PLL CLOCK DRIVER

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MPC958/D
Low Voltage PLL Clock Driver
The MPC958 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree designs. With output frequencies
of up to 200MHz and output skews of 200ps the MPC958 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
• Fully Integrated PLL
• Output Frequency up to 200MHz
• Outputs Disable in High Impedance
• LQFP Packaging
• 100ps Cycle–to–Cycle Jitter
The MPC958 has a differential LVPECL reference input along with an
external feedback input. These features make the MPC958 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will tristate the output buffers when driven “high”.
The MPC958 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50Ω transmission lines. For series terminated
50Ω lines, each of the MPC958 outputs can drive two traces giving the
device an effective fanout of 1:22. The device is packaged in a 7x7mm
32–lead LQFP package to provide the optimum combination of board
density and performance.
MPC958
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
(Int pull up)
PECL_CLK_{(Int pull down)}
PECL_CLK
(Int pull up)
FB_CLK
(Int pull up)
VCO_SEL
(Int pull up)
BYPASS
(Int pull down)
MR/OE
(Int pull up)
PLL_EN
0
Phase
Detector
LPF
VCO
1
200–400MHz
0
÷2
1
0
÷2
1
QFB
9 _Q0:8
Q9
Figure 1. Logic Diagram
06/00
© Motorola, Inc. 2000
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