MPC953 Datasheet, PDF (1/7 Pages) Motorola, Inc – LOW VOLTAGE PLL CLOCK DRIVER

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SEMICONDUCTOR TECHNICAL DATA
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Low Voltage PLL Clock Driver
The MPC953 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree designs. With output frequencies
of up to 87.5MHz and output skews of 150ps the MPC953 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
• Fully Integrated PLL
• Output Frequency up to 87.5MHz
• Outputs Disable in High Impedance
• TQFP Packaging
• 100ps Cycle–to–Cycle Jitter
The MPC953 has a differential LVPECL reference input along with an
external feedback input. These features make the MPC953 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will reset the internal counters and tristate the output buffers when
driven “high”.
If the reference clock (PECL_CLK) is lost or shut down when the
MPC953 is in phase–lock, the output frquency will slew slowly downward.
The final VCO frequency will be around TBDMHz.
The MPC953 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50Ω transmission lines. For series terminated
50Ω lines, each of the MPC953 outputs can drive two traces giving the
device an effective fanout of 1:18. The device is packaged in a 7x7mm
32–lead TQFP package to provide the optimum combination of board
density and performance.
PECL_CLK
PECL_CLK
FB_CLK
VCO_SEL
BYPASS
MR/OE
Phase
Detector
LPF
VCO
200–350MHz
÷2
Figure 1. Logic Diagram
MPC953
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
QFB
7 _Q0:6
÷4
Q7
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
9/97
© Motorola, Inc. 1997
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