MCM69R738C Datasheet, PDF (1/20 Pages) Motorola, Inc – 4M Late Write 2.5 V I/O

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MCM69R738C/D
4M Late Write 2.5 V I/O
The MCM69R738C/820C is a 4M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R820C
(organized as 256K words by 18 bits) and the MCM69R738C (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is also driven on the rising edge of CK.
The RAM uses 2.5 V inputs and outputs.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
• Byte Write Control
• Single 3.3 V +10%, –5% Operation
• 2.5 V I/O (VDDQ)
• Register to Register Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x18 or x36 Organization
• MCM69R738C/820C–4 = 4 ns
MCM69R738C/820C–4.4 = 4.4 ns
MCM69R738C/820C–5 = 5 ns
MCM69R738C/820C–6 = 6 ns
• Sleep Mode Operation (ZZ Pin)
• 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
MCM69R738C
MCM69R820C
ZP PACKAGE
PBGA
CASE 999–02
REV 1
8/13/99
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F99_{AST SRAM}
For More Information On This Product, ^{MCM69R738C•MCM69R820C}
Go to: www.freescale.com
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