MCM69R738A Datasheet, PDF (1/20 Pages) Motorola, Inc – 4M Late Write 2.5 V I/O

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
4M Late Write 2.5 V I/O
The MCM69R738A/820A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R820A
organized as 256K words by 18 bits, and the MCM69R738A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.
The RAM uses 2.5 V inputs and outputs.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
• Byte Write Control
• Single 3.3 V +10%, – 5% Operation
• 2.5 V I/O (VDDQ)
• Register to Register Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x 18 or x 36 organization
• MCM69R738A/820A–5 = 5 ns
MCM69R738A/820A–6 = 6 ns
MCM69R738A/820A–7 = 7 ns
MCM69R738A/820A–8 = 8 ns
• Sleep Mode Operation (ZZ Pin)
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
Order this document
by MCM69R738A/D
MCM69R738A
MCM69R820A
ZP PACKAGE
PBGA
CASE 999–01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
8/13/97
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MCM69R738A•MCM69R820A
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