MCM69P819 Datasheet, PDF (1/20 Pages) Motorola, Inc – 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 18 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM69P819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC™ and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P819 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
• MCM69P819–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
MCM69P819–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM69P819–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
Order this document
by MCM69P819/D
MCM69P819
ZP PACKAGE
PBGA
CASE 999–02
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 6
1/20/98
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MCM69P819
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