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MCM69F737 Datasheet, PDF (1/20 Pages) Motorola, Inc – 128K x 36 Bit Flow–Through BurstRAM Synchronous Fast Static RAM | |||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 36 Bit FlowâThrough
BurstRAM Synchronous
Fast Static RAM
The MCM69F737 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC⢠and other
high performance microprocessors. It is organized as 128K words of 36 bits
each. This device integrates input registers, a 2âbit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positiveâ
edgeâtriggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69F737 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally selfâtimed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex offâchip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as âaâ, âbâ, âcâ, and âdâ. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, a flowâthrough SRAM allows output data to simply flow freely
from the memory array.
The MCM69F737 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8â5 compatible.
⢠MCM69F737â7.5: 7.5 ns Access/8.5 ns Cycle (117 MHz)
MCM69F737â8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F737â8.5: 8.5 ns Access/11ns Cycle (90 MHz)
MCM69F737â11: 11 ns Access/20 ns Cycle (50 MHz)
⢠3.3 V + 10%, â 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
⢠ADSP, ADSC, and ADV Burst Control Pins
⢠Selectable Burst Sequencing Order (Linear/Interleaved)
⢠SingleâCycle Deselect Timing
⢠Internally SelfâTimed Write Cycle
⢠Byte Write and Global Write Control
⢠PB1 Version 2.0 Compatible
⢠JEDEC Standard 119âPin PBGA and 100âPin TQFP Packages
Order this document
by MCM69F737/D
MCM69F737
ZP PACKAGE
PBGA
CASE 999â02
TQ PACKAGE
TQFP
CASE 983Aâ01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 7
1/22/98
M© OMoTtoOroRla,OInLc.A19F98AST SRAM
MCM69F737
1
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