MCM69F536C Datasheet, PDF (1/12 Pages) Motorola, Inc – 32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 36 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69F536C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and
synchronous write enable SW are provided to allow writes to either individual
bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls DQa, SBb controls DQb, and so on. Individual bytes are written if the
selected byte writes SBx are asserted with SW. All bytes are written if either SGW
is asserted or if all SBx and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM69F536C operates from a 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
• MCM69F536C–8.5 = 8.5 ns Access / 12 ns Cycle
MCM69F536C–9 = 9 ns Access / 12 ns Cycle
MCM69F536C–10 = 10 ns Access / 15 ns Cycle
MCM69F536C–12 = 12 ns Access / 16.6 ns Cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• 5 V Tolerant on all Pins (Inputs and I/Os)
• 100–Pin TQFP Package
Order this document
by MCM69F536C/D
MCM69F536C
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 3
2/18/98
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F98_{AST SRAM}
MCM69F536C
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