MCM69D618 Datasheet, PDF (1/14 Pages) Motorola, Inc – 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM69D618/D
64K x 18 Bit Synchronous
Dual I/O, Dual Address SRAM
MCM69D618
The MCM69D618 is a 1M–bit static random access memory, organized as 64K
words of 18 bits. It features common data input and data output buffers and
incorporates input and output registers on–board with high speed SRAM.
The MCM69D618 allows the user to concurrently perform reads, writes, or
pass–through cycles in combination on the two data ports. The two address ports
(AX, AY) determine the read or write locations for their respective data ports
(DQX, DQY).
The synchronous design allows for precise cycle control with the use of an
external single clock (K). All signal pins except output enables (GX, GY) are
registered on the rising edge of clock (K).
The pass–through feature allows data to be passed from one port to the other,
in either direction. The PTX input must be asserted to pass data from port X to
port Y. The PTY will likewise pass data from port Y to port X. A pass–through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols are followed. If
both ports are read, the reads occur normally. If one port is written and the other
is read, the read from the array will occur before the data is written. If both ports
are written, only the data on DQY will be written to the array.
• Single 3.3 V ± 5% Power Supply
• Fast Access Times: 6/8 ns Max
• Throughput of 1.49 Gigabits/Second
• Single Clock Operation
• Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers
On–Chip
• 83 MHz Maximum Clock Frequency
• Self Timed Write
• Two Bi–Directional Data Buses
• Can be Configured as Separate I/O
• Pass–Through Feature
• Asynchronous Output Enables (GX, GY)
• LVTTL Compatible I/O
• Concurrent Reads and Writes
• 100–Pin TQFP Package
Suggested Applications
— ATM
— Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches
— Shared Memory
Product Family Configurations
Part
Number
MCM69D536
MCM69D618
MCM67Q709A
MCM67Q909
Dual
Address
n
n
Single
Address
Note 1
Note 1
n
n
Dual
I/O
n
n
Separate
I/O
Note 2
Note 2
n
n
Configuration
32K x 36
64K x 18
128K x 9
512K x 9
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
TQ PACKAGE
100 LEAD TQFP
CASE 983A–01
VDD
3.3 V
3.3 V
5.0 V
5.0 V
REV 5
1/16/98
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F98_{AST SRAM}
MCM69D618
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