MCM67Q709A Datasheet, PDF (1/10 Pages) Motorola, Inc – 128K x 9 Bit Separate I/O Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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128K x 9 Bit Separate I/O
Synchronous Fast Static RAM
MCM67Q709A
The MCM67Q709A is a 1,179,648–bit static random access memory, orga-
nized as 131,072 words of 9 bits. It features separate TTL input and output buff-
ers, which drive 3.3 V output levels and incorporates input and output registers
on–board with high speed SRAM. It also features transparent–write and data
pass–through capabilities.
The synchronous design allows for precise cycle control with the use of an
86 BUMP PBGA
CASE 896A–02
external single clock (K). The addresses (A0 – A16), data input (D0 – D8), data
output (Q0 – Q8), write enable (W), chip enable (E), and output enable (G), are
registered in on the rising edge of clock (K).
PIN NAMES
The control pins (E, W, G) function differently in comparison to most synchro-
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
A0 – A16 . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q709A is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package.
• Single 5 V ± 5% Power Supply
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input
SDO . . . . . . . . . . . . . . . . . Scan Data Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
• Fast Cycle Time: 10 ns Max
• Single Clock Operation
• TTL Input and Output Levels (Outputs LVTTL Compatible)
• Address, Data Input, E, W, G Registers On–Chip
PIN ASSIGNMENT
1 2 3 4 5 6 7 89
• 100 MHz Maximum Clock Cycle Time
• Self–Timed Write
A
E W VCC SDI SDO A4 A0
• Separate Data Input and Output Pins
• Transparent–Write and Pass–Through
• High Output Drive Capability: 50 pF/Output at Rated Access Time
B
A16 A14 G
K ^VSS A6 A2 ^VSS D8
C
D7 A15 NC VSS VSS VSS VSS Q8 VSS
• Boundary Scan Implementation
• PBGA Package for High Speed Operation
D _{VSS Q7 VSS VSS VSS VSS VSS Q6 D6}
E
D5 VSS VSS VSS VSS VSS VSS VSS VCC
F _{VCC Q5 VSS VSS VSS VSS VSS D4 Q4}
G
D3 Q3 VSS VSS VSS VSS VSS D2 Q2
H
VSS D1 NC VSS VSS VSS VSS D0 VSS
J
Q1 A12 A10 VSS A9 A8 A5 A1 Q0
K
A13 A11 SCK VCC SE A7 A3
TOP VIEW
86–BUMP
Not to Scale
REV 2
12/23/97
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F97_{AST SRAM}
MCM67Q709A
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