MCM67M618B Datasheet, PDF (1/12 Pages) Motorola, Inc – 64K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
MCM67M618B
The MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC™ microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig-
DQ9
nals, except output enable (G), are clock (K) controlled through posi-
DQ10
tive–edge–triggered noninverting registers.
VCC
Bursts can be initiated with either transfer start processor (TSP) or
VSS
transfer start cache controller (TSC) input pins. Subsequent burst
DQ11
addresses are generated internally by the MCM67M618B (burst
DQ12
sequence imitates that of the MC68040) and controlled by the burst
DQ13
address advance (BAA) input pin. The following pages provide more
DQ14
detailed information on burst controls.
VSS
Write cycles are internally self–timed and are initiated by the rising
VCC
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
DQ15
DQ16
DQ17
signals.
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Strobes
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• TSP, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• High Board Density 52–PLCC Package
• 3.3 V I/O Compatible
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46 DQ8
9
45 DQ7
10
44 DQ6
11
43 VCC
12
42 VSS
13
41 DQ5
14
40 DQ4
15
39 DQ3
16
38 DQ2
17
37 VSS
18
36 VCC
19
35 DQ1
20
34 DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
BAA . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
TSP, TSC . . . . . . . . . . . . . . . . Transfer Start
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be con-
nected for proper operation of the device.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
7/15/97
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F97_{AST SRAM}
MCM67M618B
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