MCM67C618A Datasheet, PDF (1/12 Pages) Motorola, Inc – 64K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM67C618A/D
64K x 18 Bit BurstRAM™
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
MCM67C618A
The MCM67C618A is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive registered output drivers onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–edge–
triggered noninverting registers.
DQ9
This device contains output registers for pipeline operations. At the ris- DQ10
ing edge of K, the RAM provides the output data from the previous cycle.
VCC
Output enable (G) is asynchronous for maximum system design flexibil-
VSS
ity.
DQ11
Burst can be initiated with either address status processor (ADSP) or ad- ^DQ12
dress status cache controller (ADSC) input pins. Subsequent burst ad- ^DQ13
dresses can be generated internally by the MCM67C618A (burst
sequence imitates that of the i486 and Pentium) and controlled by the burst
address advance (ADV) input pin. The following pages provide more de-
DQ14
VSS
VCC
DQ15
tailed information on burst controls.
DQ16
Write cycles are internally self–timed and are initiated by the rising edge _DQ17
of the clock (K) input. This feature eliminates complex off–chip write pulse
generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually write-
able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls
DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
• Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46 DQ8
9
45 DQ7
10
44 DQ6
11
43 VCC
12
42 VSS
13
41 DQ5
14
40 DQ4
15
39 DQ3
16
38 DQ2
17
37 VSS
18
36 VCC
19
35 DQ1
20
34 DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
REV 2
11/5/96
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁶AST SRAM
MCM67C618A
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