MCM67C618 Datasheet, PDF (1/12 Pages) Motorola, Inc – 64K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM67C618/D
64K x 18 Bit BurstRAM™
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
MCM67C618
The MCM67C618 is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
FN PACKAGE
technology. The device integrates input registers, a 2–bit counter, high speed
PLASTIC
SRAM, and high drive registered output drivers onto a single monolithic circuit
CASE 778–02
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
PIN ASSIGNMENTS
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered non-
inverting registers.
7 6 5 4 3 2 1 52 51 50 49 48 47
This device contains output registers for pipeline operations. At the rising edge _{DQ9 8}
of K, the RAM provides the output data from the previous cycle.
DQ10 9
Output enable (G) is asynchronous for maximum system design flexibility. VCC 10
Burst can be initiated with either address status processor (ADSP) or address VSS 11
status cache controller (ADSC) input pins. Subsequent burst addresses can be DQ11 12
generated internally by the MCM67C618 (burst sequence imitates that of the ^{DQ12 13}
46 DQ8
45 DQ7
44 DQ6
43 VCC
42 VSS
41 DQ5
i486) and controlled by the burst address advance (ADV) input pin. The following ^{DQ13 14}
40 DQ4
pages provide more detailed information on burst controls.
DQ14 15
39 DQ3
Write cycles are internally self–timed and are initiated by the rising edge of the ^{VSS 16}
38 DQ2
clock (K) input. This feature eliminates complex off–chip write pulse generation ^{VCC 17}
37 VSS
and provides increased flexibility for incoming signals.
DQ15 18
36 VCC
Dual write enables (LW and UW) are provided to allow individually writeable
DQ16
DQ17
19
20
35 DQ1
34 DQ0
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
21 22 23 24 25 26 27 28 29 30 31 32 33
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
PIN NAMES
• Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
REV 6
5/95
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MCM67C618
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