MCM67C518 Datasheet, PDF (1/12 Pages) Motorola, Inc – 32K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM67C518/D
32K x 18 Bit BurstRAM™
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
MCM67C518
The MCM67C518 is a 589,824 bit synchronous static random access memory
designed to provide a burstable, high–performance, secondary cache for the
i486™ and Pentium™ microprocessors. It is organized as 32,768 words of 18 bits,
fabricated with Motorola’s high–performance silicon–gate BiCMOS technology.
The device integrates input registers, a 2–bit counter, high speed SRAM, and
high drive registered output drivers onto a single monolithic circuit for reduced
FN PACKAGE
PLASTIC
CASE 778–02
parts count implementation of cache data RAM applications. Synchronous de-
sign allows precise cycle control with the use of an external clock (K). BiCMOS
PIN ASSIGNMENTS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered non-
7 6 5 4 3 2 1 52 51 50 49 48 47
inverting registers.
DQ9 8
46 DQ8
This device contains output registers for pipeline operations. At the rising edge ^{DQ10 9}
45 DQ7
of K, the RAM provides the output data from the previous cycle.
Output enable (G) is asynchronous for maximum system design flexibility.
VCC 10
VSS ₁₁
44 DQ6
43 VCC
Burst can be initiated with either address status processor (ADSP) or address
DQ11
DQ12
12
13
status cache controller (ADSC) input pins. Subsequent burst addresses can be _{DQ13 14}
42 VSS
41 DQ5
40 DQ4
generated internally by the MCM67C518 (burst sequence imitates that of the _{DQ14 15}
39 DQ3
i486) and controlled by the burst address advance (ADV) input pin. The following _{VSS 16}
38 DQ2
pages provide more detailed information on burst controls.
VCC 17
37 VSS
Write cycles are internally self–timed and are initiated by the rising edge of the _{DQ15 18}
36 VCC
clock (K) input. This feature eliminates complex off–chip write pulse generation DQ16 19
35 DQ1
and provides increased flexibility for incoming signals.
DQ17 20
34 DQ0
Dual write enables (LW and UW) are provided to allow individually writeable
21 22 23 24 25 26 27 28 29 30 31 32 33
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
PIN NAMES
• Single 5 V ± 5% Power Supply
• Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
REV 3
5/95
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MCM67C518
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