MCM67B618B Datasheet, PDF (1/11 Pages) Motorola, Inc – 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
MCM67B618B
The MCM67B618B is a 1,179,648–bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentiumr microprocessors. The MCM67B618B (organized as
65,536 words by 18 bits) is fabricated using Motorola’s high–performance
silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit
counter, high speed SRAM, and high drive capability outputs onto a single
monolithic circuit for reduced parts count implementation of cache data RAM
applications. Synchronous design allows precise cycle control with the use of an
external clock (K). BiCMOS circuitry reduces the overall power consumption of
the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either address status processor (ADSP)
DQ9
or address status cache controller (ADSC) input pins. Subsequent
burst addresses can be generated internally by the MCM67B618B
(burst sequence imitates that of the i486 and Pentium) and controlled
DQ10
VCC
VSS
DQ11
by the burst address advance (ADV) input pin. The following pages pro-
DQ12
vide more detailed information on burst controls.
DQ13
Write cycles are internally self–timed and are initiated by the rising
DQ14
edge of the clock (K) input. This feature eliminates complex off–chip
VSS
write pulse generation and provides increased flexibility for incoming
VCC
signals.
DQ15
Dual write enables (LW and UW) are provided to allow individually
DQ16
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
DQ17
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
• Single 5 V ±5% Power Supply
• Fast Access Time: 9 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46 DQ8
9
45 DQ7
10
44 DQ6
11
43 VCC
12
42 VSS
13
41 DQ5
14
40 DQ4
15
39 DQ3
16
38 DQ2
17
37 VSS
18
36 VCC
19
35 DQ1
20
34 DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . +5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be con-
nected for proper operation of the device.
i486 is a trademark and Pentium is a registered trademark of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
9/21/99
©_MOMo_Tto_Oro_Rla,_OIn_Lc._A19_F99_{AST SRAM}
MCM67B618B
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