MCM67B518 Datasheet, PDF (1/12 Pages) Motorola, Inc – 32K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM67B518/D
32K x 18 Bit BurstRAM™
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
MCM67B518
The MCM67B518 is a 589,824 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentium™ microprocessors. It is organized as 32,768 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for re-
duced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67B518 (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
7 6 5 4 3 2 1 52 51 50 49 48 47
DQ9 8
46 DQ8
DQ10 9
VCC 10
VSS ₁₁
DQ12 12
DQ11 13
45 DQ7
44 DQ6
43 VCC
42 VSS
41 DQ5
DQ13 14
40 DQ4
DQ14 15
39 DQ3
VSS 16
VCC 17
DQ15 18
DQ16 19
38 DQ2
37 VSS
36 VCC
35 DQ1
DQ17 20
34 DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
REV 2
5/95
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MCM67B518
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