MCM67A618B Datasheet, PDF (1/12 Pages) Motorola, Inc – 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
MCM67A618B
The MCM67A618B is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in-
put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup-
ported by multiple power pins.
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually
DQ9
DQ10
writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW
controls DQ9 – DQ17 (the upper bits).
Six pair of power and ground pins have been utilized and placed on
VCC
VSS
DQ11
the package for maximum performance.
DQ12
The MCM67A618B will be available in a 52–pin plastic leaded chip
DQ13
carrier (PLCC).
DQ14
This device is ideally suited for systems that require wide data bus
VSS
widths, cache memory, and tag RAMs.
VCC
• Single 5 V ± 5% Power Supply
DQ15
DQ16
• Fast Access Times: 10/12/15 ns Max
DQ17
• Byte Writeable via Dual Write Enables
• Separate Data Input Latch for Simplified Write Cycles
• Address and Chip Enable Input Latches
• Common Data Inputs and Data Outputs
• Output Enable Controlled Three–State Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46 DQ8
9
45 _DQ7
10
44 _DQ6
11
43 _VCC
12
42 _VSS
13
41 _DQ5
14
40 _DQ4
15
39 _DQ3
16
38 _DQ2
17
37 _VSS
18
36 _VCC
19
35 _DQ1
20 ₂₁
22 23
24 25 26
27 28
34
29 30 31 32 33
DQ0
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Higher Byte Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be con-
nected for proper operation of the device.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
7/16/97
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁷AST SRAM
MCM67A618B
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