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MCM63Z836 Datasheet, PDF (1/36 Pages) Motorola, Inc – 256K x 36 and 512K x 18 Bit ZBT Fast Static RAM | |||
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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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256K x 36 and 512K x 18 Bit
ZBTr Fast Static RAM
MCM63Z836
MCM63Z918
The ZBT RAM is an 8Mâbit synchronous fast static RAM designed to provide
Zero Bus Turnaroundr. The ZBT RAM allows 100% use of bus cycles during
backâtoâback read/write and write/read cycles. The MCM63Z836 (organized as
256K words by 36 bits) and the MCM63Z918 (organized as 512K words by 18
bits) are fabricated in Motorolaâs high performance silicon gate CMOS tech-
nology. This device integrates input registers, an output register, a 2âbit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in communication applications. Synchronous design allows precise cycle
control with the use of an external positiveâedgeâtriggered clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positiveâ
edgeâtriggered noninverting registers.
Write cycles are internally selfâtimed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex offâchip write pulse generation
and provides increased timing flexibility for incoming signals. Write data is
supplied to the memory one cycle after the write sequence initiation for the flowâ
through device, and two cycles after the write sequence initiation for the pipelined
device.
For flowâthrough read cycles, the SRAM allows output data to simply flow freely from the memory
array. For pipelined read cycles, the SRAM output data is temporarily stored by an edgeâtriggered
output register and then released to the output buffers at the next rising edge of clock (CK).
The MCM63Z836 and MCM63Z918 operate from a 3.3 V core power supply and all outputs oper-
ate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC Standard JESD8âA and
JESD8â5 compatible.
⢠3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
⢠MCM63Z836 / 918â7 = 7 ns FlowâThrough Access / 2.6 ns Pipelined Access (225 MHz)
MCM63Z836 / 918â8 = 8 ns FlowâThrough Access / 3 ns Pipelined Access (200 MHz)
MCM63Z836 / 918â8.5 = 8.5 ns FlowâThrough Access / 3.5 ns Pipelined Access (166 MHz)
⢠Selectable Read/Write Functionality (FlowâThrough/Pipelined)
⢠Selectable Burst Sequencing Order (Linear/Interleaved)
⢠Internally SelfâTimed Write Cycle
⢠TwoâCycle Deselect (Pipelined)
⢠Byte Write Control
⢠ADV Controlled Burst
⢠Simplified JTAG
⢠100âPin TQFP and 119âBump PBGA Packages
TQ PACKAGE
TQFP
CASE 983Aâ01
ZP PACKAGE
PBGA
CASE 999â02
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 4
12/20/99
©MMOoTtoOrolRa,OIncL.A19F99AST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM63Z836â¢MCM63Z918
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