MCM63R836A Datasheet, PDF (1/21 Pages) Motorola, Inc – 8M Late Write HSTL

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MCM63R836A/D
8M Late Write HSTL
MCM63R836A
MCM63R918A
The MCM63R836A/918A is an 8M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM63R918A
(organized as 512K words by 18 bits) and the MCM63R836A (organized as
256K words by 36 bits) are fabricated in Motorola’s high performance silicon gate
copper CMOS technology.
. _{The differential clock (CK) inputs control the timing of read/write operations of}
INC the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
R, selects are registered. An internal buffer and special logic enable the memory to
TO ^{accept write data on the rising edge of CK, a cycle after address and control}
C _{signals. Read data is also driven on the rising edge of CK.}
DU _{The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)}
ON and output voltage (VDDQ) gives the system designer greater flexibility in
IC _{optimizing system performance.}
EM The synchronous write and byte enables allow writing to individual bytes or
S _{the entire word.}
LE _{The impedance of the output buffers is programmable, allowing the outputs to}
CA _{match the impedance of the circuit traces which reduces signal reflections.}
EES ^{• Byte Write Control}
FR • 2.5 V – 5% to 3.3 V + 10% Operation
Y _{• HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)}
D ^B • HSTL — User Selectable Input Trip–Point
IVE ^{• HSTL — Compatible Programmable Impedance Output Drivers}
H _{• Register to Register Synchronous Operation}
ARC ^{• Boundary Scan (JTAG) IEEE 1149.1 Compatible}
• Differential Clock Inputs
• Optional x18 or x36 Organization
• MCM63R836A / 918A–3.0 = 3.0 ns
MCM63R836A / 918A–3.3 = 3.3 ns
MCM63R836A / 918A–3.7 = 3.7 ns
MCM63R836A / 918A–4.0 = 4.0 ns
• Sleep Mode Operation (ZZ pin)
• 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic
Ball Grid Array (PBGA)
FC PACKAGE
PBGA
CASE 999D–01
10/16/00
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A20_F00_{AST SRAM}
For More Information On This Product, ^{MCM63R836A•MCM63R918A}
Go to: www.freescale.com
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