MCM63P737K Datasheet, PDF (1/20 Pages) Motorola, Inc – 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MCM63P737K/D
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static
RAMs designed to provide a burstable, high performance, secondary cache. The
MCM63P737K (organized as 128K words by 36 bits) and the MCM63P819K
(organized as 256K words by 18 bits) integrate input registers, an output register,
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)
controlled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P737K and MCM63P819K
(burst sequence operates in linear or interleaved mode dependent upon the state
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P737K and MCM63P819K operate from a 3.3 V core power
supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and
outputs are JEDEC standard JESD8–5 compatible.
• MCM63P737K / MCM63P819K–166 = 3.5 ns Access / 6 ns Cycle (166 MHz)
MCM63P737K / MCM63P819K–150 = 3.8 ns Access / 6.7 ns Cycle (150 MHz)
MCM63P737K / MCM63P819K–133 = 4 ns Access / 7.5 ns Cycle (133 MHz)
• 3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages
MCM63P737K
MCM63P819K
TQ PACKAGE
TQFP
CASE 983A–01
ZP PACKAGE
PBGA
CASE 999–02
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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For More Information On This Product, ^{MCM63P737K•MCM63P819K}
Go to: www.freescale.com
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