MCM63P636 Datasheet, PDF (1/27 Pages) Motorola, Inc – 64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
64K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P636 is a 2M–bit synchronous fast static RAM designed to provide
burstable, high performance, secondary cache for advanced microprocessors.
It is organized as 64K words of 36 bits each. This device integrates input regis-
ters, an output register, a 2–bit address counter, and a high speed SRAM onto
a single monolithic circuit for reduced parts count in cache data RAM applica-
tions. Synchronous design allows for precise cycle control with the use of an ex-
ternal clock (K) and external strobe clock (SK).
Addresses (SA), data inputs (DQx), and all control signals are clock (K)
controlled through positive–edge–triggered noninverting registers. Data strobes
STRBA, STRBA, STRBB, and STRBB are strobe clock (SK) controlled through
positive–edge–triggered non–inverting registers. Strobe clock, 180 degrees out
of phase with clock (K), is only used with the data strobes such that they are
centered with data output on read cycles.
Burst sequences are initiated with ADS input pin, and subsequent burst
addresses are generated internally by MCM63P636.
Write cycles are internally self–timed and are initiated with address and control
logic by the rising edge of the clock (K) input. This feature eliminates complex
off–chip write pulse generation and provides increased timing flexibility for
incoming signals. Special logic enables the memory to accept data on the rising
edge of clock (K) a cycle after address and control signals.
For read cycles, the SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the
second rising edge of clock (K) for a read latency of three cycles. Data strobes
rise and fall with SRAM output to help external devices receiving the data to
latch the data.
The MCM63P636 operates from a 3.3 V core power supply, a 2.0 V input power
supply, and a 2.0 V I/O power supply. These power supplies are designed so that
power sequencing is not required.
• MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)
MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)
MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)
• 3.3 V ± 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply
• Internally Self–Timed Late Write Cycle
• Three–Cycle Single–Read Latency
• Strobe Clock Input and Data Strobe Output Pins
• On–Chip Output Enable Control
• On–Chip Burst Advance Control
• Four–Tick Burst
• Power–On Reset Pin
• Low Power Stop Clock Operation
• Boundary Scan (PBGA Only)
• JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages
Order this document
by MCM63P636/D
MCM63P636
ZP PACKAGE
PBGA
CASE 1107–01
TQ PACKAGE
TQFP
CASE 983A–01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
3/16/98
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁸AST SRAM
MCM63P636
1