MCM63F733A Datasheet, PDF (1/16 Pages) Motorola, Inc – 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the PowerPC™ and
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con-
sumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM63F733A operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.
• MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)
MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)
• 3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Single–Cycle Deselect
• Sleep Mode (ZZ)
• 100–Pin TQFP Package
Order this document
by MCM63F733A/D
MCM63F733A
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
3/20/98
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F98_{AST SRAM}
MCM63F733A
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