MCM6343 Datasheet, PDF (1/10 Pages) Motorola, Inc – 256K x 15 Bit 3.3 V Asynchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6343/D
Product Preview
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
MCM6343
The MCM6343 is a 4,194,304–bit static random access memory organized as
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6343 is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB
controls the upper bits DQ8 to DQ15.
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package
and a 44–lead TSOP Type II package.
• Single 3.3 V ± 0.3 V Power Supply
• Fast Access Time: 12/15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Data Byte Control
• Fully Static Operation
• Power Operation: 250/240/230 mA Maximum, Active AC
• Commercial and Standard Industrial Temperature Option: – 40 to + 85°C
BLOCK DIAGRAM
G OUTPUT
ENABLE
BUFFER
A ADDRESS
BUFFERS
18
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
9
8
9
ROW COLUMN
DECODER DECODER
HIGH
BYTE ⁸
OUTPUT
BUFFER
E
CHIP
ENABLE
BUFFER
W ^WRITE
ENABLE
BUFFER
256K x 16
BIT
MEMORY
ARRAY
SENSE
16 _AMPS
HIGH
8 _BYTE 8
WRITE
DRIVER
LOW
8
BYTE ⁸
OUTPUT
BUFFER
LB
BYTE
UB ENABLE
BUFFER
LOW
8 _BYTE 8
WRITE
HIGH BYTE WRITE ENABLE
DRIVER
LOW BYTE WRITE ENABLE
YJ PACKAGE
400 MIL SOJ
CASE 919–01
TS PACKAGE
TSOP TYPE II
CASE 924A–02
PIN ASSIGNMENT
A1
A2
A3
A4
A5
44 A
43 A
42 A
41 G
40 UB
E6
DQ0 7
DQ1 8
DQ2 9
DQ3 10
39 LB
38 DQ15
37 DQ14
36 DQ13
35 DQ12
VDD 11
VSS 12
DQ4 13
DQ5 14
DQ6 15
DQ7 16
W 17
A 18
A 19
A 20
A 21
A 22
34 VSS
33 VDD
32 DQ11
31 DQ10
30 DQ9
29 DQ8
28 NC
27 A
26 A
25 A
24 A
23 A
PIN NAMES
A0 – A17 . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQ0 – DQ15 . . . . . . . . . . Data Input/Output
VDD . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
2/10/98
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁸AST SRAM
MCM6343
1