MCM6323A Datasheet, PDF (1/12 Pages) Motorola, Inc – 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-
age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
• Single 3.3 V ± 0.3 V Power Supply
• Fast Access Time: 10, 12, 15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Data Byte Control
• Fully Static Operation
• Power Operation: 140/135/130 mA Maximum, Active AC
• Industrial Temperature Option: – 40 to + 85°C
Part Number: SCM6323AYJ10A
BLOCK DIAGRAM
G OUTPUT
ENABLE
BUFFER
A _ADDRESS
BUFFERS
16
E
CHIP
ENABLE
BUFFER
W ^WRITE
ENABLE
BUFFER
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
7
8
9
ROW COLUMN
DECODER DECODER
8
64K x 16
BIT
MEMORY
ARRAY
SENSE
16 _AMPS
8
HIGH
BYTE ^{8 DQb}
OUTPUT
8
BUFFER
HIGH
BYTE ⁸
WRITE
DRIVER
LOW
BYTE ^{8 DQa}
OUTPUT
8
BUFFER
LB
BYTE
UB ENABLE
BUFFER
8
HIGH BYTE WRITE ENABLE
LOW
BYTE ⁸
WRITE
DRIVER
LOW BYTE WRITE ENABLE
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
REV 1
10/17/97
MCM6323A
YJ PACKAGE
400 MIL SOJ
CASE 919–01
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–01
PIN ASSIGNMENT
A1
A2
A3
A4
A5
E6
DQa 7
DQa 8
DQa 9
DQa 10
VDD 11
VSS 12
DQa 13
DQa 14
DQa 15
DQa 16
W 17
A 18
A 19
A 20
A 21
NC 22
44 A
43 A
42 A
41 G
40 UB
39 LB
38 DQb
37 DQb
36 DQb
35 DQb
34 VSS
33 VDD
32 DQb
31 DQb
30 DQb
29 DQb
28 NC
27 A
26 A
25 A
24 A
23 NC
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQa . . . . . . . . . . . . Lower Data Input/Output
DQb . . . . . . . . . . . . Upper Data Input/Output
VDD . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F97_{AST SRAM}
MCM6323A
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